Sidewall insulated resistive memory devices

ABSTRACT

To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive memory device is provided. The resistive memory device includes an active region having resistance properties that can be modified to store one or more data bits in the resistive memory device, and at least one sidewall portion of the active region comprising a dopant configured to suppress conductance paths in the active region proximate to the at least one sidewall portion. The resistive memory device includes terminals configured to couple the active region to associated electrical contacts.

TECHNICAL FIELD

Aspects of the disclosure are related to the field of data storage andresistive random access memory in data storage devices.

TECHNICAL BACKGROUND

Computer and network data systems such as personal computers,workstations, server systems, and cloud storage systems, typicallyinclude data storage devices for storing and retrieving data. These datastorage devices can include hard disk drives (HDDs), solid state storagedrives (SSDs), tape storage devices, optical storage drives, hybridstorage devices that include both rotating and solid state data storageelements, and other mass storage devices. Recently, new storagetechnologies have been developed which employ resistive memory elements.These resistive memory elements can include resistive random-accessmemory (RRAM or ReRAM), which are types of non-volatile random accessmemory that store data by altering a resistance of a solid-statematerial. However, resistive memory elements can be difficult tomanufacture and incorporate into memory devices.

Overview

To provide enhanced data storage devices and systems, various systems,architectures, apparatuses, and methods, are provided herein. In a firstexample, a resistive memory device is provided. The resistive memorydevice includes an active region having resistance properties that canbe modified to store one or more data bits in the resistive memorydevice, and at least one sidewall portion of the active regioncomprising a dopant configured to suppress conductance paths in theactive region proximate to the at least one sidewall portion. Theresistive memory device includes terminals configured to couple theactive region to associated electrical contacts.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the disclosure can be better understood with referenceto the following drawings. The components in the drawings are notnecessarily to scale, emphasis instead being placed upon clearlyillustrating the principles of the present disclosure. Moreover, in thedrawings, like reference numerals designate corresponding partsthroughout the several views. While several embodiments are described inconnection with these drawings, the disclosure is not limited to theembodiments disclosed herein. On the contrary, the intent is to coverall alternatives, modifications, and equivalents.

FIG. 1 is a system diagram illustrating a resistive memory array.

FIG. 2 illustrates manufacture of resistive memory arrays.

FIG. 3 illustrates a resistive memory device.

FIG. 4 illustrates manufacture of resistive memory arrays.

FIG. 5 is a system diagram illustrating a resistive memory array.

FIG. 6 illustrates manufacture of resistive memory arrays.

FIG. 7 illustrates manufacture of resistive memory arrays.

FIG. 8 illustrates a resistive memory device.

DETAILED DESCRIPTION

High-density storage devices employ a variety of storage technologies.Magnetic storage devices have been employed in many storage systems,such as hard disk drives with rotating magnetic media. More recently,solid state storage devices, such as flash drives employing NAND flashor other semiconductor-based memory technologies have become popular asassociated densities have increased. Other storage technologies, such asoptical and non-rotating magnetic technologies are also employed.However, resistive non-volatile memory (NVM) technologies have becomepossible using materials which have alterable electrical properties,such as electrical resistances, that persist after application of anelectric current. These resistive memory devices include memristors andother related devices. Memristors typically comprise two-terminalelectrical components which relate electric charge to magnetic fluxlinkage, where an electrical resistance of a memristor depends upon aprevious electrical current passed by the memristor. Although memristorscan be incorporated into non-volatile memories, it has been difficult toincorporate arrays of these memristors into storage devices, in part dueto difficulty in achieving addressable memory arrays.

As will be seen herein, various enhanced architectures and devicesemploy two-terminal resistive memory devices and three-terminalresistive memory devices as non-volatile storage elements. In someexamples, these resistive memory devices comprise three-terminal devicesthat include a gate, source, and drain terminals, with the gate terminalemployed to alter resistance properties, such as electrical resistances,of an active channel between the source and drain terminals. Thesethree-terminal devices can be referred to as resistive random-accessmemory (ReRAM) devices or ReRAM elements. However, the enhancementsherein apply to two-terminal (source-active channel-drain) andthree-terminal devices (source-active channel-drain with gate) resistivememory devices. As discussed below, resistive memory elements/devicesinclude resistive memory material in an active channel portionpositioned between source and drain terminals. The resistive memorymaterial comprises flux linkage-controlled resistor material, and theelements described herein can be formed from various metal oxidesthrough reduction or oxidation processes.

FIG. 1 is presented to illustrate exemplary three-terminal resistivememory devices in an arrayed configuration. Two-terminal devices caninstead be employed, and these will be further illustrated in at leastFIG. 2. Turning now to FIG. 1, FIG. 1 is a system diagram illustrating aresistive memory array. Specifically, FIG. 1 shows array 150 comprisinga plurality of ReRAM elements 151 and interconnect 152. ReRAM elements151 are interconnected via interconnect elements and form wordlines inthe ‘vertical’ direction and bitlines in the ‘horizontal’ direction,although different configurations are possible. Devices 101 and 102 showtwo examples of ReRAM elements 151 which can be employed in array 150,although variations are possible. Device 101 illustrates a ReRAM devicewithout sidewall doping, while device 102 illustrates a device withsidewall doping.

Array 150 can be built up vertically (i.e. in a ‘z’ direction) from awafer or substrate, such as shown for wafer 590 in FIG. 5. Array 150 canbe built onto one or more semiconductor logic layers, metallizationlayers, and interconnect layers, which are shown in later examples. Theunderlying logic and interconnect can be related to a logic circuits,processors, control systems, or other elements which can at leastcontrol the elements of memory layers formed on top of semiconductorlayers. For example, when a semiconductor wafer is employed for creationof logic circuitry and associated interconnect, then one or more layersof resistive memory can be formed on top of logic circuitry andassociated interconnect using techniques found in semiconductor waferprocessing and microfabrication, such as photo-lithography, diffusing,deposition, epitaxial growth, etching, annealing, and ion implanting,among others.

Turning now to device 101, this device includes active channel 110,source terminal 111, drain terminal 112, gate terminal 113, andinterconnect 114. Active channel 110 comprises resistive memory materialfor forming a non-volatile memory cell. Active channel 110 can haveassociated resistance properties altered using gate terminal 113, andthese resistance properties can be used to store one or more bits ofdata, such as predetermined resistance levels corresponding to one ormore bits of data. However, irregularities and surface defects insidewalls 116 of device 101 can lead to pathways which are of higherconductance or lower resistance than a central part of active channel110. This can cause ‘shorting’ of current between source terminal 111and drain terminal 112 and inaccurate storage and retrieval ofassociated data bits.

Device 102 includes active channel 120, source terminal 121, drainterminal 122, gate terminal 123, and interconnect 124. Active channel120 comprises resistive memory material for forming a non-volatilememory cell. Active channel 120 can have associated resistanceproperties altered using gate terminal 123, and these resistanceproperties can be used to store one or more bits of data. In device 102,sidewalls 125 have had a dopant introduced. This dopant can provideenhanced operation of active channel 120 and device 102 by at leastcompensating for irregularities and defects at the sidewalls of activechannel 120. Specifically, the dopant can increase a dielectric propertyof the sidewalls to reduce conductance paths across the sidewalls andpush current flow into a more central area 126 of active channel 120.Further examples of manufacturing techniques for ReRAM arrays andindividual memory devices are discussed in the following examples below.

During operation, control system 160 can be employed to control theelements of ReRAM array 150. Control system 160 can be included tocontrol each of the resistive memory elements for reading and writing ofdata bits into associated memory cells. Control system 160 can be formedin logic on the same wafer as ReRAM array 150 or included in separatecircuitry or logic devices.

In write operations, control system 160 can apply a voltage the gates ofeach ReRAM element over associated gate links which will alterresistance properties of resistive non-volatile memory (NVM) material inthe associated active channels. Altered resistance properties can beused to store data bits in memory cells, with values of the resistanceproperties indicating various bit values, such as a binary ‘1’ or‘0’—although multi-level bit logic can be employed to store many bitsper memory cell depending upon the resistance properties.

In read operations, control system 160 can measure a series resistanceacross all of the ReRAM elements using interconnect links 152. Thisseries resistance might not indicate the data stored by individualmemory cells, as all three memory cells in this example would bemeasured in series. Control system 160 can also measure individualmemory cells by measuring resistances through individual gates andinterconnect 152. Further resistance measurements can be employed. Thesevarious resistance measurements can be processed to identify data bitsstored in each memory cell, which can include comparing the seriesresistance of the entire array to individual gate-selected resistancemeasurements.

Turning now to the elements of control system 160, FIG. 1 illustrates acontrol system or controller which can be employed to interface with oneor more resistive memory arrays, such as array 150 or individual devices101 or 102. Control system 160 is representative of any logic, controlsystems, or collection of logic and systems in which the variousresistive memory read, write, and other operational architectures,scenarios, and processes disclosed herein may be implemented. Forexample, control system 160 can be employed in any of the sublayer logiconto which memory array 150 is formed. Features of control system 160can be incorporated into further devices and systems, such as externalcontrollers, logic modules, microprocessors, computing devices, ordistributed computing devices, as well as any variation or combinationthereof.

Control system 160 may be implemented as a single apparatus, system, ordevice or may be implemented in a distributed manner as multipleapparatuses, systems, or devices. For example, control system 160 cancomprise one or more application-specific integrated circuits (ASICs),field-programmable gate arrays (FPGA), or discrete logic and associatedcircuitry, including combinations thereof. Although not shown in FIG. 1,control system 160 can include communication interfaces, networkinterfaces, user interfaces, and other elements for communicating with ahost system over communication link 165. Control system 160 mayoptionally include additional devices, features, or functionality notdiscussed for purposes of brevity.

Control system 160 can also comprise or communicate with one or moremicrocontrollers or microprocessors with software or firmware includedon computer-readable storage media devices. If software or firmware isemployed, the computer-readable storage media devices may includevolatile and nonvolatile, removable and non-removable media implementedin any method or technology for storage of information, such as computerreadable instructions, data structures, program modules, or other data.Examples of storage media include random access memory, read onlymemory, magnetic disks, resistive memory devices, ReRAM devices, opticaldisks, flash memory, virtual memory and non-virtual memory, magneticcassettes, magnetic tape, magnetic disk storage or other magneticstorage devices, or any other suitable storage media.

Control system 160 includes various controller portions to controlresistive memory arrays, namely write controller 161, read controller162, and optionally data processor 163. Write controller 161 writes datainto resistive memory devices discussed herein, such as by using gatefeatures or gate terminals of resistive memory devices. Write controlsignaling can include bitlines and wordlines which are used to uniquelyaddress a resistive memory device to write data into that resistivememory device. In some examples, only entire wordlines are addressableand thus an entire wordline of data is written into associated resistivememory devices simultaneously. Read controller 162 reads data stored inresistive memory devices. The read process can include measuringresistance properties of ones of the resistive memory devices. Forexample, read controller 162 is communicatively coupled to ends ofwordlines or the resistive memory devices and measure at least a seriesresistance property of each of the wordlines. Read controller 162 canalso be communicatively coupled to ends of the bitlines of the resistivememory devices and individually select ones of the bitlines to measurean associated resistance property of a subset of the resistive memorydevices as a series resistance property through a bitline-selected gateportion and a selected wordline. Read controller 162 can determine datastored by ones of the resistive memory devices by at least processingthe series resistance property of a wordline that contains the at leastthe resistive memory devices being read and a resistance property of asubset of the resistive memory devices being read. Other techniques canbe employed to measure and read data from each of the resistive memorydevices. Data processor 163 is optionally included to further processdata, such as to arrange data into logical arrangements including words,pages, and the like, before transfer to a host over link 165. Dataprocessor 163 can also be configured to perform encoding/decoding orencryption/decryption operations with respect to the data stored in anassociated resistive memory array.

FIGS. 2-4 each show various cross-sectional, side, and top views ofmanufacturing processes and structures for forming a resistive memoryarray, such as the memory array shown in FIG. 1, although variations arepossible. It should be noted that the thicknesses and other dimensionsof the various elements, layers, and materials employed herein candepend on properties of the specific materials employed, propertiesdesired for the devices, manufacturing techniques employed, among otherconsiderations.

In FIG. 2, three configurations 201, 202, and 203 are illustrated. Inthe configurations shown in FIG. 2, a ‘top’ side of a resistive memorymaterial is proximate to a source terminal and a ‘bottom side’ of theresistive memory material is proximate to a drain terminal. It should beunderstood that the top, sidewalls, and bottom portions of the resistivememory material can be in different configurations depending onorientation of the resistive memory device, preferred conductiondirection, gate configurations, or other considerations. Other elementsto form a resistive memory device, such as gate elements or substrates,are omitted from some of the configurations for clarity.

Configuration 201 illustrates a cross-sectional view of an exampleresistive memory device with un-doped sidewalls of an active region,such as before a doping process occurs. Configuration 201 includesresistive NVM material 210 forming an active region or active channelfor storing one or more bits of data in a resistive memory material,along with proximate source 211 and drain 212 terminals. Inconfiguration 201, irregular sidewalls 218 are shown which can lead toconductance paths 219 forming near the sidewalls indicated inconfiguration 201. Conductance paths 219 can lead to memory performancedegradation of the associated resistive memory device due in part to‘shorting’ currents encountered during read or write processes andassociated inaccurate storage and retrieval of data bits.

Configuration 202 illustrates a cross-sectional view of an exampleresistive memory device with doped sidewalls, such as after dopant 227is introduced into resistive NVM material 220. Configuration 202includes resistive NVM material 220, source terminal 221, drain 222. Inconfiguration 202, sidewalls 228 have dopant 227 introduced. This dopantcan provide enhanced operation of an active channel of resistive NVMmaterial 220 by at least compensating for irregularities and defects atthe sidewalls of the active channel of resistive NVM material 220.Specifically, the dopant can increase a dielectric property of thesidewalls to reduce conductance paths proximate to the sidewalls andpush current flow into a more central area of the active channel ofresistive NVM material 210. Configuration 202 shows conductance paths229 in a more central region of the active channel of resistive NVMmaterial 220.

Configuration 203 illustrates a cross-sectional view of an exampleresistive memory array with doped sidewalls 238 in each resistive memorydevice. Three resistive memory devices 250-252 are shown inconfiguration 203, although other examples can include a differentnumber of devices. Moreover, configuration 203 shows vertically orientedresistive memory devices, with insulator material on at least thehorizontal sides of each device. The insulator material can be partiallyenveloping of each device, such as on a single side, or can fullyenvelop each resistive memory device, such as shown in FIG. 5. Infurther examples, the insulator material can include gate material orgate portions proximate to the active channels that form bitlines for awordline of three-terminal resistive memory devices, and more than onevertical layer of resistive memory devices can be employed.

Each resistive memory device includes an active channel (230), sourceterminal (231), drain terminal (232), insulator material (233), anddoped sidewalls (238). Doped sidewalls 238 can be formed by etching outvias or voids into insulator material 223, then introducing a dopantonto the sidewalls of the voids, such as by using chemical depositiontechniques to apply the dopant to the sidewalls of the voids or byfilling the voids with the dopant and re-etching smaller voids to leavea portion of the dopant behind on the sidewalls. Heat can be appliedonce the dopant is deposited or filled to diffuse the dopant into theactive channels and create doped sidewalls 238. Other techniques orprocesses can be employed to introduce the dopant material intosidewalls of the active channel of each resistive memory device.

Source and drain terminal elements discussed herein, such as source 231and drain 232, can be formed from various materials. In a first example,similar or the same material used for resistive NVM material 220 oractive channel 230 can be altered chemically to form terminals orelectrodes suitable for source and drain elements. In this firstexample, further material can be introduced into layers or portions ofresistive NVM material to modify a resistance or conductance propertyinto a conductive state above a desired conductance levels or belowdesired resistance levels. This process can be a diffusion process tointroduce more metallic materials of a metal oxide to enhanceconductivity of the metal oxide material. In examples where tantalumoxide is employed for the resistive NVM material, further tantalum canbe included to form a source or drain element. In examples, wherehafnium oxide is employed for the resistive NVM material, furtherhafnium can be included to form the source or drain elements. In asecond example, an oxidation range of metal oxide material comprisingresistive NVM material is altered into a high oxidation state or lowreduction state, so the metal oxide exhibits conductive properties.Other example materials are possible and suitable for source and drainelements, such as metallized material or metal material, polycrystallinesilicon material, or others, including combinations thereof.

In some examples, insulator material 233 comprises an electricalinsulator or dielectric material, such as a metal oxide materialincluding hafnium oxides (HfO_(n)), tantalum oxides (TaO_(m)), zirconiumoxides (ZrO_(p)), or any other suitable metal oxide, where ‘n’ and ‘p’can vary based on levels of oxidation and reduction of the basechemical/metal. These metal oxides can comprise ‘binary’ metal oxides.Binary metal oxides discussed herein have properties that can be altereddepending upon a level of oxidation, specifically resistive memoryproperties, conductive properties, or insulating properties. In a firstoxidation range comprising a low oxidation state or highly reducedstate, the binary metal oxide exhibits insulating properties. Otherinsulating materials can be employed, such as polycrystalline siliconmaterial, silicon dioxide, or other materials.

Configuration 203 also shows the resistive memory array formed as one ormore layers onto a plurality of sublayers. The resistive memory arraycan be built up vertically (i.e. in a ‘z’ direction) from a wafer orsubstrate, such as shown for wafer 590 in FIG. 5. The resistive memoryarray can be formed onto one or more sublayers, such as bulk 240,metallization layers 241, logic layers 242, and semiconductor substratelayers 243, among other layers. The underlying logic and interconnectcan be related to a logic circuits, processors, control systems, orother elements which can at least control the elements of the resistivememory array layers formed on top of semiconductor layers. For example,when a semiconductor wafer is employed for creation of logic circuitryand associated interconnect, then one or more layers of resistive memorycan be formed on top of logic circuitry and associated interconnectusing techniques found in semiconductor wafer processing andmicrofabrication, such as photo-lithography, diffusing, deposition,epitaxial growth, etching, annealing, and ion implanting, among others.

FIG. 3 illustrates further example configurations of resistive memorydevices and processes for manufacturing such devices. Specifically, FIG.3 illustrates configuration 301 and 302 for a lateral ReRAM device whichcan be a single device or part of a larger array of devices. Inconfiguration 301, a side cross-sectional view is shown. Configuration302 illustrates a top view of the ReRAM device with optional gate 313omitted for clarity. It should be understood that the top, sidewalls,and bottom portions of the resistive memory material can be in differentconfigurations depending on orientation of the ReRAM device, preferredconduction direction, gate configurations, or other considerations.Other elements to form a ReRAM device, such as substrates andinterconnect, are omitted from the configurations for clarity.

In configuration 301, a side view of a ReRAM device is shown thatincludes bottom insulation portion 318, resistive NVM material 310, andtop insulation portion 317. Source terminal 311 and drain terminal 312are coupled to respective portions of resistive NVM material 310, andoptional gate terminal 313 is positioned proximate to an active channel330 of the ReRAM device. Resistive properties of the resistive NVMmaterial can be altered according to a voltage applied to gate 313,which changes resistive properties of active channel 330 and stores oneor more bits of data in the ReRAM device. Source 311, drain 312, andgate 313 can be coupled via interconnect to further ReRAM devices inarrayed configurations or to control circuitry, including combinationsthereof.

Configuration 301 illustrates doped sidewalls, such as after dopant 319is diffused into outer walls of resistive NVM material 310. This dopantcan provide enhanced operation of active channel 330 of resistive NVMmaterial 310 by at least compensating for irregularities and defects atthe sidewalls of active channel 330 and resistive NVM material 310.Specifically, the dopant can increase a dielectric property of thesidewalls to reduce conductance paths proximate to the sidewalls andpush current flow into a more central area of the active channel ofresistive NVM material 310.

Top insulation portion 317 can protect active channel 330 or otherportions of resistive NVM material 310 from contaminants, furtherstructures, metallization, migration of metal ions, atmosphere, oxygen,or other materials, including combinations thereof. Top insulationportion 317 can be formed with a passivation layer created in activechannel 330. This passivation layer provides a layer of isolationbetween active channel 330. Bottom insulation portion 318 and topinsulation portion 317 can be formed from similar or differentmaterials.

In some examples, top insulation portion 317 and bottom insulationportion 318 each comprise an electrical insulator or dielectricmaterial, such as a metal oxide material including hafnium oxides(HfO_(n)), tantalum oxides (TaO_(m)), zirconium oxides (ZrO_(p)), or anyother suitable metal oxide, where ‘n’ and ‘p’ can vary based on levelsof oxidation and reduction of the base chemical/metal. These metaloxides can comprise ‘binary’ metal oxides. Binary metal oxides discussedherein have properties that can be altered depending upon a level ofoxidation, specifically resistive memory properties, conductiveproperties, or insulating properties. In a first oxidation rangecomprising a low oxidation state or highly reduced state, the binarymetal oxide exhibits insulating properties. In a second oxidation rangecomprising a high oxidation state or low reduction state, the binarymetal oxide exhibits conductive properties. The second oxidation rangecan be employed for forming terminals or electrode portions, such assource and drain terminals.

In a third oxidation range, or middle state, the binary metal oxide willexhibit resistive memory properties which can be altered to store bitsof data, and can be employed as resistive NVM material 310. Whenemployed in three-terminal resistive memory devices, these materials cancomprise flux linkage controlled resistor materials, where gate portionsinfluence device operation by a voltage applied to the material or acurrent through the material. Other examples can have the resistivememory material comprising simple or complex transition metal oxides(i.e. titanium, zirconium, tungsten, ruthenium, yttrium, scandium,cobalt, nickel, copper), perovskites, delafossites, or mixed oxides,including combinations thereof. Further example resistive memorymaterials can include ones formed with doped CuInO₂, Mott transitionmaterials, or Schottky barrier materials. Other materials are possible,including combinations thereof.

Gate portions discussed herein, such as optional gate 313, can comprisen-type or p-type semiconductor material, polycrystalline siliconmaterial, or other material. Isolating gate oxides can be includedbetween gate portions and associated memory cell portions. Gate portionscan comprise a material that forms a rectifying junction with thematerial of the associated memory cell (such as an active channel of theresistive memory device), which isolates the gate and acts as aselector, such as an n-type semiconductor or an n-type polycrystallinesilicon material. Other examples have the gate material comprising ap-type material, which would form a PN rectifying junction from memorycell-to-gate. PN junctions can be fabricated not only with classicalsemiconductors, but also with metal oxides. When PN junctions areemployed, a resistance level can be measured through the gate associatedwith a memory cell, as current can flow from the resistive memorymaterial of the memory cell through the gate, but not in reverse due tothe PN junction. In other examples, no PN rectifying junction is formedbetween gate and memory cell. In this other example, the gate is notelectrically isolated from the channel, and resistance values for amemory cell can be measured from gate-to-channel.

FIG. 4 illustrates a process of manufacturing filled-via memory devicesas one example of a resistive memory devices and resistive memory array.In FIG. 4, three configurations are shown to illustrate various steps ina manufacturing process for a resistive memory array. The associatedresistive memory devices can comprise two-terminal (source-activechannel-drain) or three-terminal devices (source-active channel-drainwith gate). Gate portions in FIG. 4 are omitted for clarity. It shouldbe understood that further quantities of devices can be included andmany layers of the devices can be formed by stacking individual arrays.

In configuration 401, a layer of bottom terminal material 412 isestablished below a layer of insulator material 418. Bottom material 412can comprise metallization in some examples or instead can comprise ametal oxide in a high oxidation state or low reduction state, such astantalum oxide or hafnium oxide in a high oxidation state or lowreduction state. Insulator material 418 comprises an electricallyinsulating material, such as a high-K material. In this example,insulator material comprises zirconium or an oxide of zirconium,although other materials can be employed.

In configuration 402, vias 430 have been formed in insulator materiallayer 418 to reach bottom terminal layer 412. Vias 430 can be formedusing various semiconductor micromachining techniques ormicrofabrication techniques, such as milling, patterned masking/etching,or other techniques. Each via 430 will define a resistive memory cell ora ReRAM device.

In configuration 403, vias 430 have each been filled with resistivememory material, specifically, resistive NVM material 410 and a topterminal layer 411 has been established over insulator material layer418 and NVM material 410. Insulator material 418 at the interface withresistive NVM material 410 forms insulated sidewalls 420. Heating orother processes can be performed after resistive NVM material 410 isfilled into vias 430 to diffuse a portion of insulator material 418 intoresistive NVM material 410. As can be seen in configuration 403, currentpaths 421 are shown as forming in a central portion of each memory cellformed by resistive NVM material 410. These current paths would bepreferred during operation between top terminal 411 and bottom terminal412 instead of along sidewalls of resistive NVM material 410. Insulatormaterial 418 compensates for any sidewall material irregularities orsurface defects in resistive NVM material 410 from milling or depositionof resistive NVM material 410. Surface defects or sidewallirregularities in resistive NVM material 410 can lead to unwantedconduction paths along the sidewalls of resistive NVM material 410.Further diffusion of insulator material 418 into resistive NVM material410 can further reduce sidewall conduction paths.

Thus, in configuration 403 of FIG. 4, three resistive memory devices 450have been formed, with source terminals formed by the top terminal layerand drain terminals formed by the bottom terminal layer. Active zones oractive channels of each resistive memory device is formed from resistivememory material deposited into vacated vias formed into insulatormaterial. Further layers of these devices can be stacked vertically toform many layers of resistive memory devices. Moreover, optional gateelements (not shown in FIG. 4) can be included proximate to the activechannels of resistive memory material to electrically alter resistanceproperties of the active channels to store bits of data. Stored data canbe read by detecting resistance of each memory cell by drawing currentthrough the associated active channels. In two-terminal resistive memorydevices, the gate elements can be omitted.

FIG. 5 is a system diagram illustrating an example resistive memoryarray. Specifically, ReRAM array 501 is shown in FIG. 5 as comprisingfifteen (15) ReRAM devices in a vertically stacked arrangement. Otherquantities of ReRAM devices can be included and multiple horizontallayers of ReRAM devices can be employed, such as to have both rows andcolumns of ReRAM devices forming a three-dimensional (3D) arrangement.ReRAM device 502 is shown as an exemplary device found in ReRAM array501, although variations are possible. ReRAM device 503 is shown as a 3Disometric solid illustration of an ReRAM device which can be employed inarray 501.

Turning first to array 501, the vertical arrangement has active channelsof columns of ReRAM device coupled vertically to form individualwordlines of a memory array, with source and drain terminals integratedinto the vertical wordlines for each device (see device 503). Thevertical arrangement also has gate portions of rows of ReRAM devicescoupled horizontally to form individual bitlines of a memory array.Using a selected wordline and bitline, a control system can selectivelywrite and read from ones of the ReRAM devices, such as in addressablememory configurations.

Current 535 is shown as able to flow through each vertical columncomprising the active channels and source/drain terminal for each ReRAMdevice of the column. Moreover, since the ReRAM devices in array 501employ sidewall doping as discussed herein, conduction paths for current535 form generally in the central portions of the active channels ofeach ReRAM device instead of along the sidewalls.

Device 502 is a detailed view of any of the ReRAM devices in array 501.Device 502 includes active channel 510, source terminal 511, drainterminal 512, gate terminal 513, and doped sidewalls 515. Gate terminal513 surrounds a central active channel in device 502, and the side viewof device 502 in FIG. 5 illustrates this feature.

Further detail is shown in device 503, with gate terminal 513surrounding a central active channel 510 which itself is surrounded bydoped sidewalls 515. Device 503 further shows an alternative examplewith interconnect portions 540 that include source 511 and drain 512.Memory cell 541 is surrounded by gate 513 and gate 513 can alterresistance properties of memory cell 541 proximate to gate 513.

In FIG. 5, the active channels 510 of each ReRAM device comprise a metaloxide material, such as an oxide of tantalum or an oxide of hafnium.Doped sidewalls 515 comprise a layer of zirconium-rich material, whichcan be a distinct layer deposited onto sidewalls of active channelmaterial or an at least partially diffused layer of dopant into thesidewalls of active channel material. Further active channel and dopantmaterial are discussed herein.

FIG. 6 illustrates manufacture of resistive memory arrays in an example.The associated resistive memory arrays can include two-terminal orthree-terminal devices. FIG. 6 illustrates deposited sidewall devices.In FIG. 6, a first configuration 601 illustrates a layered configurationestablished by layering different materials onto a substrate or bulk,such as optional bulk 619. Other substrates can be employed, such aswhen arrays of resistive memory devices are formed onto sublayers oflogic and related interconnect. Bottom terminal layer 612 is formed ontop of bulk 619, resistive NVM material 610 is formed on top of layer612, and top terminal layer 611 is formed on top of layer 610. Theselayers can be formed using various semiconductor manufacturing processesor material deposition techniques, such as atomic layer deposition(ALD), chemical vapor deposition (CVD), sputtering, gas/plasmadeposition, or other processes, including combinations thereof.

Configuration 602 shows vias 617 etched or milled through layers 611,610, and 612. Vias 617 can be formed into at least a portion of layer612, or can be formed through the entire thickness of layer 612.Configuration 603 shows sidewall material deposited as insulatormaterial 618 into each via, specifically, onto the sidewalls formed byvias 617. Insulator material 618 can be any of the dopant materialdiscussed herein, such as a zirconium material. One specific example ofa zirconium material includes zirconium oxide (ZrO₂). Insulator material618 can include high-K dielectrics. In one example, resistive NVMmaterial 610 comprises tantalum oxide, and insulator material 618comprises hafnium-doped tantalum oxide. In another example, resistiveNVM material 610 comprises tantalum oxide, and insulator material 618comprises zirconium-doped tantalum oxide or zirconium-doped hafniumoxide. In yet another example, resistive NVM material 610 compriseshafnium oxide, and insulator material 618 comprises tantalum-dopedhafnium oxide. Other sidewall/dopant material can be employed, such asthose discussed herein. Moreover, after deposition, insulator material618 can be diffused into sidewalls of each via (which includes diffusioninto a portion of material 610) using various diffusion techniques, suchas heating. It should be understood that usage of tantalum oxide orhafnium oxide refers to various oxides of tantalum or hafnium, withamounts of oxidation selected to provide for resistive memory propertiesof the associated memory cell. Insulator material 618 can be depositedusing various material deposition techniques, such as ALD, CVD,sputtering, gas/plasma deposition, or other processes, includingcombinations thereof.

Thus, in FIG. 6, at least two resistive memory devices 650 have beenformed. Each resistive memory device has a first terminal formed by aportion of layer 611 and a second terminal formed by a portion of layer612. Source and drain designations can correspond to ones of thefirst/second terminals. Once material 618 is deposited and optionallydiffused, then the remaining void portions of vias 617 can be filledwith further material, such as an insulating material. In some examples,material 618 is deposited to substantially fill each via 617, andadditional material is not employed.

FIG. 7 illustrates manufacture of resistive memory arrays in an example.The associated resistive memory arrays can include two-terminal orthree-terminal devices. FIG. 7 illustrates re-deposited sidewalldevices. In FIG. 7, a first configuration 701 illustrates a layeredconfiguration established by layering different materials onto asubstrate or bulk, such as optional bulk 719. Other substrates can beemployed, such as when arrays of resistive memory devices are formedonto sublayers of logic and related interconnect, which is shown inconfiguration 702 in FIG. 7. Bottom terminal layer 712 is formed on topof bulk 719. Insulator material layer 718 is formed on top of layer 712.Resistive NVM material layer 710 is formed on top of layer 718, and topterminal layer 711 is formed on top of layer 710. These layers can beformed using various semiconductor manufacturing processes or materialdeposition techniques, such as atomic layer deposition (ALD), chemicalvapor deposition (CVD), sputtering, gas/plasma deposition, or otherprocesses, including combinations thereof.

Insulator material layer 718 can be any of the dopant material discussedherein, such as a zirconium material. One specific example of azirconium material includes zirconium oxide (ZrO₂). Insulator materiallayer 718 can include high-K dielectrics. In one example, resistive NVMmaterial 710 comprises tantalum oxide, and insulator material 718comprises hafnium-doped tantalum oxide. In another example, resistiveNVM material 710 comprises tantalum oxide, and insulator material 718comprises zirconium-doped tantalum oxide or zirconium-doped hafniumoxide. In yet another example, resistive NVM material 710 compriseshafnium oxide, and insulator material 718 comprises tantalum-dopedhafnium oxide. It should be understood that usage of tantalum oxide orhafnium oxide refers to various oxides of tantalum or hafnium, withamounts of oxidation selected to provide for resistive memory propertiesof the associated memory cell. Other material can be employed, such asthose discussed herein.

Configuration 702 shows vias 717 etched or milled through layers 711,710, 718, and 712. Vias 717 can be formed into at least a portion oflayer 712, or can be formed through the entire thickness of layer 712.The process of forming vias 717 through each layer can re-depositmaterial of a current layer being etched or milled onto sidewalls of theassociated via. The stackup of the layers of configuration 701 are suchthat when vias 717 are etched/milled, material from layer 718 isre-deposited onto sidewalls of the vias. Thus, material is re-depositedfrom a layer underlying resistive NVM material 710 onto sidewalls ofeach via and likewise onto sidewalls formed into resistive NVM material710. In some examples, layer 718 comprises a zirconium (Zr) materialwhich is subsequently oxidized (ZrO₂) after re-deposition onto thesidewalls of each via. Configuration 702 shows sidewall materialre-deposited as insulator material 718 into each via, specifically, ontothe sidewalls formed by vias 717. Moreover, after deposition, insulatormaterial 718 can be diffused into sidewalls of each via (which includesdiffusion into a portion of material 710) using various diffusiontechniques, such as heating.

Thus, in FIG. 7, at least two resistive memory devices 750 have beenformed. Each device 750 has a first terminal formed by a portion oflayer 711 and a second terminal formed by a portion of layer 712. Sourceand drain designations can correspond to ones of the first/secondterminals. Once material 718 is re-deposited and optionally diffused,then the remaining void portions of vias 717 can be filled with furthermaterial, such as an insulating material.

Configuration 702 also shows the resistive memory array formed as one ormore layers onto a plurality of sublayers. The resistive memory arraycan be built up vertically (i.e. in a ‘z’ direction) from a wafer orsubstrate, such as shown for wafer 590 in FIG. 5. The ReRAM array can beformed onto one or more sublayers, such as metallization layers 780,logic layers 781, and semiconductor substrate layers 782, among otherlayers. The underlying logic and interconnect can be related to a logiccircuits, processors, control systems, or other elements which can atleast control the elements of the resistive memory array layers formedon top of semiconductor layers. For example, when a semiconductor waferis employed for creation of logic circuitry and associated interconnect,then one or more layers of resistive memory can be formed on top oflogic circuitry and associated interconnect using techniques found insemiconductor wafer processing and microfabrication, such asphoto-lithography, diffusing, deposition, epitaxial growth, etching,annealing, and ion implanting, among others.

FIG. 8 illustrates a resistive memory device in an example. FIG. 8includes configurations for manufacturing processes employed information of two top point resistive memory devices 850. Inconfiguration 801, a first layer is formed comprising bottom terminallayer 812 which can be shared among the resistive memory devices. Asecond layer is formed onto layer 812 comprising resistive NVM materiallayer 810 which houses active zones 820 or active channels for theresistive memory devices. A third layer is formed onto layer 810comprising top terminal layer 811. First layer 811 and second layer 812can comprise materials described herein for source and drain terminals.It should be understood that positioning of source and drain layers andassociated terminals can be swapped in other examples.

In configuration 802, insulator material 818 is introduced to formsource terminals 821 and form device separation elements 830 whichseparate source terminals of individual resistive memory devices 850.Insulator material 818 can provide enhanced operation of an active zoneof resistive memory devices by at least compensating for irregularitiesand defects at the periphery of active zones 820 comprising resistiveNVM material. Specifically, insulator material 818 can increase adielectric property of the periphery of active zones 820 to reduceconductance paths proximate to the periphery and push current flow intoa more central area of the active zone of each resistive memory device.

Insulator material 818 can be any of the dopant material discussedherein, such as a zirconium material. One specific example of azirconium material includes zirconium oxide (ZrO₂). Insulator material818 can include high-K dielectrics. In one example, resistive NVMmaterial 810 comprises tantalum oxide, and insulator material 818comprises hafnium-doped tantalum oxide. In another example, resistiveNVM material 810 comprises tantalum oxide, and insulator material 818comprises zirconium-doped tantalum oxide or zirconium-doped hafniumoxide. In yet another example, resistive NVM material 810 compriseshafnium oxide, and insulator material 818 comprises tantalum-dopedhafnium oxide. After introduction, insulator material 818 can bediffused into surrounding materials of layer 810 and source terminals821 using various diffusion techniques, such as heating. It should beunderstood that usage of tantalum oxide or hafnium oxide refers tovarious oxides of tantalum or hafnium, with amounts of oxidationselected to provide for resistive memory properties of the associatedmemory cell.

Elements 830 can be formed using various processes. In a first exampleprocess, insulator material 818 is introduced into layer 811, such as bymasked/patterned diffusion of insulator material 818 into selectiveportions of layer 811. This selective introduction of material 818 canalter chemical and electrical properties of layer 811 at portions oflayer 811 where material 818 is introduced. These altered properties canprovide isolation and electrical insulation, while pushing conductancepaths for resistive memory devices into central portions of associatedactive zones 820. In a second example process, portions of layer 811 areetched or otherwise removed in a selective matter, such as using maskedetching or selective milling. Insulator material 818 can then bedeposited into voids created during the etching/milling process.Insulator material 818 can be deposited using various materialdeposition techniques, such as ALD, CVD, sputtering, gas/plasmadeposition, or other processes, including combinations thereof.

Thus, two resistive memory devices 850 are created in configuration 802,with current flow shown with associated dashed arrows in FIG. 8.Additionally, gate elements can be optionally formed proximate to activezones 820 to electrically modify resistances or resistance properties ofassociated ones of active zones 820 and store one or more bits of datausing the modified resistance properties of the active zones.

The included descriptions and figures depict specific embodiments toteach those skilled in the art how to make and use the best mode. Forthe purpose of teaching inventive principles, some conventional aspectshave been simplified or omitted. Those skilled in the art willappreciate variations from these embodiments that fall within the scopeof the invention. Those skilled in the art will also appreciate that thefeatures described above can be combined in various ways to formmultiple embodiments. As a result, the invention is not limited to thespecific embodiments described above, but only by the claims and theirequivalents.

1. A resistive memory device, comprising: an active region havingresistance properties that can be modified to store one or more databits in the resistive memory device; at least one sidewall portion ofthe active region comprising a dopant configured to suppress conductancepaths in the active region proximate to the at least one sidewallportion; and terminals configured to couple the active region toassociated electrical contacts.
 2. The resistive memory device of claim1, comprising: the at least one sidewall portion of the active regionfurther configured to constrain current flow to a central portion of theactive region.
 3. The resistive memory device of claim 1, wherein thedopant increases dielectric properties of the sidewall portion of theactive region, and the dopant comprises a dielectric material diffusedinto the sidewall portion of the active region.
 4. The resistive memorydevice of claim 1, further comprising: a gate portion proximate to theactive region and configured to modify the resistance properties of theactive region responsive to voltages applied to the gate portion.
 5. Theresistive memory device of claim 1, wherein the active region comprisesan oxide of tantalum, and wherein the dopant comprises at least one ofan oxide of hafnium and an oxide of zirconium.
 6. The resistive memorydevice of claim 1, wherein a first of the terminals comprises a sourceterminal proximate to a first sidewall of the active region, wherein asecond of the terminals comprises a drain terminal proximate to a secondsidewall of the active region different than the first sidewall, whereinthe at least one sidewall portion of the active region comprising thedopant comprises at least a third sidewall of the active regiondifferent than the first and second sidewalls.
 7. The resistive memorydevice of claim 1, wherein the active region comprises resistive memorymaterial deposited into a via feature created in a layer of materialcomprising the dopant, and wherein at least a portion of the dopant isdiffused into the resistive memory material at the at least one sidewallportion of the active region.
 8. The resistive memory device of claim 1,wherein the active region comprises a layer of resistive memory materialhaving material comprising the dopant deposited in a via featureestablished in the layer of resistive memory material, and wherein atleast a portion of the dopant is diffused into the resistive memorymaterial at the at least one sidewall portion of the active region. 9.The resistive memory device of claim 1, wherein the active regioncomprises a layer of resistive memory material having the dopantdeposited along a sidewall of a via feature established in the layer ofresistive memory material, the dopant redeposited during creation of thevia feature into a sublayer comprising the dopant.
 10. A method ofmanufacturing a resistive memory device, the method comprising: formingan active region comprising a resistive memory material havingresistance properties that can be electrically modified to store one ormore data bits; forming at least one sidewall portion in the activeregion by at least introducing a dopant configured to suppressconductance paths in the active region proximate to the at least onesidewall portion; forming terminals against associated sides of theactive region different than the at least one sidewall portion.
 11. Themethod of claim 10, wherein the dopant increases dielectric propertiesof the at least one sidewall portion.
 12. The method of claim 10,wherein the dopant comprises a dielectric material diffused into the atleast one sidewall portion of the active region.
 13. The method of claim10, wherein the active region comprises an oxide of tantalum, andwherein the dopant comprises at least one of an oxide of hafnium and anoxide of zirconium.
 14. The method of claim 10, wherein a first of theterminals comprises a source terminal proximate to a first sidewall ofthe active region, wherein a second of the terminals comprises a drainterminal proximate to a second sidewall of the active region differentthan the first sidewall, wherein the at least one sidewall portion ofthe active region comprising the dopant comprises at least a thirdsidewall of the active region different than the first and secondsidewalls.
 15. The method of claim 10, wherein forming the active regioncomprises depositing resistive memory material deposited into a viafeature created in a layer of material comprising the dopant, andwherein at least a portion of the dopant is diffused into the resistivememory material at the at least one sidewall portion of the activeregion.
 16. The method of claim 10, wherein forming the active regioncomprises first depositing a layer comprising the resistive memorymaterial, establishing a via feature in the layer comprising theresistive memory material, depositing the dopant onto a wall of the viafeature, and diffusing at least a portion of the dopant from the wall ofthe via feature into the resistive memory material at the at least onesidewall portion of the active region.
 17. The method of claim 10,wherein forming the active region comprises first depositing a layercomprising the resistive memory material, establishing a via feature inthe layer comprising the resistive memory material, redepositing thedopant onto a wall of the via feature from creation of the via featureinto a sublayer comprising the dopant, and diffusing at least a portionof the dopant from the wall of the via feature into the resistive memorymaterial at the at least one sidewall portion of the active region. 18.A solid state data storage array, comprising: one or more wordlines eachcomprising resistive random access memory (ReRAM) elements connected inseries by interconnect, the interconnect of each of the wordlinescomprising material introduced between adjacent ReRAM elements toestablish a conductive link between the adjacent ReRAM elements; each ofthe ReRAM elements comprising an active channel between a source anddrain, the active channel comprising resistive memory material withresistance properties of the resistive memory material corresponding todata stored by the associated ReRAM element; each of the active channelsof the ReRAM elements comprising at least one sidewall portioncomprising a dopant configured to suppress conductance paths in theassociated active channel proximate to the at least one sidewallportion; each of the ReRAM elements comprising a gate portion positionedproximate to the active channel and configured to alter the resistanceproperties of the active channel responsive to at least voltages appliedto the gate portion.
 19. The solid state data storage array of claim 18,wherein the active channel of each of the ReRAM elements comprises anoxide of tantalum, and wherein the dopant comprises at least one of anoxide of hafnium and an oxide of zirconium
 20. The solid state datastorage array of claim 18, comprising: a semiconductor sublayer on whichthe ReRAM elements are layered, the semiconductor sublayer comprisinglogic circuitry configured to control at least the solid state datastorage array.